Aggregate throughput of up to 12 Gbits/second ¦ Second-generation HOTLink® technology ¦ Compliant to multiple standards . SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ESCON, and Gigabit Ethernet (IEEE802.3z) . 10 bit uncoded data or 8B/10B coded data ¦ Truly independent channels . Each channel is able to: • Perform reclocker function • Operate at a different signaling rate • Transport a different data format ¦ Internal phase-locked loops (PLLs) with no external PLL components ¦ Selectable dif

BiCMOS technology Functional Description The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are independent and can operate simultaneously at different rat

Low power, 350 nA RTC current . Capacitor or battery backup for RTC ¦ Watchdog timer ¦ Clock alarm with programmable interrupts ¦ Hands off automatic STORE on power down with only a small capacitor ¦ STORE to QuantumTrap™ initiated by software, device pin, or on power down ¦ RECALL to SRAM initiated by software or on power up ¦ Infinite READ, WRITE, and RECALL cycles ¦ High reliability . Endurance to 200K cycles . Data retention: 20 years at 55°C ¦ Single 3V operation with tolerance of +20%, –10

The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V. Document Number: 38-07138 Rev. *B Page 3 of 19 [+] Feedback CY7B991 CY7B992 Figure 1 shows the typical outputs with FB connected to a zero skew output.[4] Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output t –

Selectable skew to 18 ns . Inverted and non-inverted . Operation at 1.2 and 1.4 input frequency . Operation at 2x and 4x input frequency (input as low as 3.75 MHz) ¦ Zero input to output delay ¦ 50% duty cycle outputs ¦ Outputs drive 50. terminated lines ¦ Low operating current ¦ 32-pin PLCC/LCC package ¦ Jitter < 200 ps peak-to-peak (< 25 ps RMS) Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These

. BiCMOS technology Functional Description The CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292 and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel

Document Number: 38-07408 Rev. *D Page 4 of 14 [+] Feedback CY7B9911V 3.3V RoboClock+™ Document Number: 38-07408 Rev. *D Page 5 of 14 Operational Mode Descriptions Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of the outputs are aligned and drive a terminated transmission line to an independent load. The FB input is tied to

Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. 10. Applies to REF and FB inputs only. 11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2ns or less and output loading as sho

terminated lines ¦ Low operating current ¦ 24-pin SOIC package ¦ Jitter:<200 ps peak to peak, <25 ps RMS Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50.. They deliver minimal and specified output skews and full swing logic levels (CY

XBUF CPLL SPLL UPLL OSC. CPUCLK CLKA CLKB CLKC CLKD MUX OE CLKF /1,2,4 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40/48,52,96,104 /2,3,4 /1,2,4,8 (8 BIT) (8 BIT) (10 BIT) Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07189 Rev. *C Revised September 16, 2008 [+] Feedback CY2291 Pinouts Pin Definitions Figure 1. CY2291- 20-pin SOIC 32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32XI