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manual abstract
Low power, 350 nA RTC current . Capacitor or battery backup for RTC ¦ Watchdog timer ¦ Clock alarm with programmable interrupts ¦ Hands off automatic STORE on power down with only a small capacitor ¦ STORE to QuantumTrap™ initiated by software, device pin, or on power down ¦ RECALL to SRAM initiated by software or on power up ¦ Infinite READ, WRITE, and RECALL cycles ¦ High reliability . Endurance to 200K cycles . Data retention: 20 years at 55°C ¦ Single 3V operation with tolerance of +20%, –10% ¦ Commercial and industrial temperature ¦ 48-Pin SSOP package (ROHS compliant) Functional Description The Cypress CY14B101K combines a 1 Mbit nonvolatile static RAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. The Real Time Clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator. The alarm function is programmable for one time alarm or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control. STORE/ RECALL CONTROL POWER CONTROL SOFTWARE DETECT STATIC RAM ARRAY 1024 X 1024 QuantumTrap 1024 x 1024 STORE RECALL COLUMN IO COLUMN DEC ROW DECODERINPUT BUFFERS OE CE WE HSB VCC VCAP A15 -A0 A0 A1 A2 A3 A4 A10 A11 A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RTC MUX A16 -A0 x1 x2 INT VRTCbat VRTCcap Logic Block Diagram Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-06401 Rev. *I Revised February 24, 2009 [+] Feedback CY14B101K Pin Configurations Figure 1. 48-Pin SSOP VCAP 1 48 VCC A16 2 47 A15 A14 3 46 HSB A12 4 45 WE A7 5 44 A13 A6 6 43 A8 A5 7 42 A9 INT 8 41 NC A4 NC 9 10 48-SSOP 40 39 A11 NC NC 11 38 NC NC 12 Top View 37 NC VSS 13 36 VSS NC 14 (Not To Scale) 35 NC VRTCbat 15 34 VRTCcap DQ0 16 33 DQ6 A3 17 32 OE A2 18 31 A10 A1 19 30 CE A0 20 29 DQ7 DQ1 21 28 DQ5 DQ2 22 27 DQ4 x1 23 26 DQ3 x2 24 25 VCC Table 1. Pin Definitions Pin Name Alt IO Type Description A0 – A16 Input Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM. DQ0 – DQ7 Input Output Bidirectional Data IO Lines. Used as input or output lines depending on operation NC No Connect No Connects. This pin is not connected to the die WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. OE G Input Output Enable, Active LOW. The active low OE input enables the data output buffers during READ cycles. Deasserting OE high causes the IO pins to tri-state. X1 Output Crystal Connection Drives crystal on start up. X2 Input Crystal Connection for 32.768 kHz crystal. VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCbat is used) VRTCbat Power Supply Battery Supplied Backup RTC Supply Voltage. (Left unconnected if VRTCcap is used) INT Output Interrupt Output. Program to respond to the clock alarm, the watchdog timer, and the power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain). VSS Ground Ground for the Device. Must be connected to ground of the system. VCC Power Supply Power Supply Inputs to the Device. HSB Input Output Hardware Store Busy. When LOW this output indicates a Hardware Store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). VCAP Power Supply AutoStore™ Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Document Number: 001-06401 Rev. *I Page 2 of 28 [+] Feedback CY14B101K automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Device Operation The CY14B101K nvSRAM consists of two functional components paired in the same physical cell. The components are SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM WRITE A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE or WE go HIGH at the end of the cycle. The data on the common IO pins DQ0–7 is written into the memory if the data is valid tSD before the end of a WE controll...