P u ll-u p Freq. Phase Modulating VCO Post CLKOUT Detector Charge Pump Waveform Dividers Divider Feedback Divider PLL GND VDD . M N Clock Input (SSCG Output) REFOUT Logic Control SDATA SCLOCK PWRDWN# Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07531 Rev. ** Revised March 18, 2003 [+] Feedback CY25822-2 Pin Description Pin No. Pin Name Pin Type Pin Description 1 CLKIN Input 48-MHz or 66-MHz Clock Input. 2 VDD Power Power Supply fo

*B Revised October 26, 2005 [+] Feedback CY25566 Pin Description Pin Name Type Description 1 XIN/CLKIN I Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. 2 REFOFF I Input pin enables REFOUT clock at pin 3. REFOFF 400K. internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled. 3 REFOUT O Buffered, non-modulated output clock derived from XIN/CLKIN input frequency. There is a 180° phase shift fro

–65°C to + 150°C Input Voltage Relative to Vdd:.............................. Vdd + 0.3V Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, TA = 0°C to +70°C and CL = 15 pF (unless otherwise noted) Parameter Description Conditions Min. Typ. Max. Unit Vdd Power Supply Range 2.97 3.3 3.63 V VINH Input HIGH Voltage S0 Input 0.85 Vdd Vdd Vdd V VINM Input MIDDLE Voltage S0 Input 0.40 Vdd 0.50 Vdd 0.60 Vdd V VINL Input LOW Voltage S0 Input 0.0 0.0 0.15 Vdd V VOH1 Output HIGH Voltage IOH = 4 ma, S

. *B Revised April 11, 2006 [+] Feedback CY25818/19 . Pin Description Pin Name Description 1 XIN/CLK Clock, Crystal, or Ceramic Resonator Input Pin. 2 Vss Power Supply Ground. 3 S0 Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. 4 SSCLK Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to Table 2 for the amount of modulation (Spread%). 5 REFCLK Unmodulated Reference Clock Output. The unmodulated output frequency is the same as t

Absolute Maximum Ratings this circuit. For proper operation, VIN and VOUT should be constrained to the range, VSS < (VIN or VOUT) < VDD. All digital inputs are tied high or low internally. Refers to electrical specifications for operating supply range. Parameter Description Min. Max. Unit VDD Operating Voltage 3.0 6.0 VDC VIRvss Input, relative to VSS –0.3 VDD + 0.3 VDC VORvss Output, relative to VSS –0.3 VDD + 0.3 VDC TOP Temperature, Operating 0 +70 °C TST Temperature, Storage –65 +150 °C TJ T

outputs • 6- to 82-MHz operating frequency range • Modulates external clocks including crystals, crystal oscillators, or ceramic resonators • Programmable modulation with simple R-C external loop filter (LF) • Center spread modulation • 3V-5V power supply • TTL-/CMOS-compatible outputs • Low short-term jitter • Low-power Dissipation — 3.3 VDC = 37 mW – typical — 5.0 VDC = 115 mW – typical • Available in 8-pin SOIC and TSSOP packages Applications • Desktop/notebook computers • Printers, copiers,

*F Page 4 of 12 [+] Feedback FS781/82/84 Table 4. Modulation Rate Divider Ratios S1 S0 Input Frequency Range (MHz) Modulation Divider Number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 SSCG Modulation Profile The digital control inputs S0 and S1 determine the modulation frequency of FS781/2/4 products. The input frequency is divided by a fixed number, depending on the operating range that is selected. The modulation frequency of the FS78x can be determined from Table 4. To

Notes 9. Jitter measured at crossing points and is the absolute value of the worst case deviation. 10. Measured at crossing points. 11. If input modulation is used; input modulation is allowed but not required. 12. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. 13. VOX

Device Comparison ¦ Meets Rambus® Extended Data Rate (XDR™) clocking requirements ¦ 25 ps typical cycle-to-cycle jitter . –135 dBc/Hz typical phase noise at 20 MHz offset ¦ 100 or 133 MHz differential clock input CY24271 CY24272 SDA hold time = 300 ns (SMBus compliant) SDA hold time = 0 ns (I2C compliant) RRC = 200. typical (Rambus standard drive) RRC = 295. minimum (Reduced output drive) ¦ 300–667 MHz high speed clock support ¦ Quad (open drain) differential output drivers ¦ Supports frequency

XBUF CPLL SPLL UPLL OSC. CPUCLK CLKA CLKB CLKC CLKD MUX OE CLKF /1,2,4 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40/48,52,96,104 /2,3,4 /1,2,4,8 (8 BIT) (8 BIT) (10 BIT) Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07189 Rev. *C Revised September 16, 2008 [+] Feedback CY2291 Pinouts Pin Definitions Figure 1. CY2291- 20-pin SOIC 32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32XI