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• For more information, refer to the AMM Help File, Chassis Trigger page. U2781A User’s Guide Features and Functions To PC with AMM USB Interface MASTER Module MASTER Module SSI Signals SSI Signals FPGA FPGA 55-pin 55-pin 55-pin Connectors 55-pin 55-pin 55-pin 55-pin 55-pin Connectors Connectors Connectors Connectors Connectors Connectors Connectors SSI Trigger Bus Chassis SLAVE module 1 SLAVE module 1 SLAVE module 2 SLAVE module 2 SSI Signals SSI Signals FPGA FPGA 55-pin 55-pin Connectors Connectors Figure 2-4 Synchronization between modules in the chassis U2781A User’s Guide Features and Functions Single Master–multiple Slaves In this configuration, only one Master module is allowed to send the SSI trigger event to the receiving Slave modules. Configuration with Agilent U2300A, U2500A, and U2600A Series DAQ only When there is one or more U2300A, U2500A, or U2600A Series DAQ in the SSI configuration, SSI allows users to set only one of the modules as MASTER and others as SLAVE through AMM. Alternatively, users can also set this configuration using the SCPI commands. NOTE Refer to U2300A, U2500A, and U2600A Series DAQ Programmer's Reference. Figure 2-5 Single Master–multiple Slave triggering with DAQ U2781A User’s Guide Features and Functions Configuration with combination of Agilent U2300A, U2500A, U2600A Series DAQ and U2700A Series modular products With one DAQ configured as Master, all of the other U2700A Series modular devices can only be configured as Slave to receive the event of the signal as shown in Table 2-2. Figure 2-6 Single Master–multiple Slave triggering Table 2-3 shows some examples of supported and not supported configurations. U2781A User’s Guide Features and Functions Table 2-3 Example of configurations for single Master-multiple Slaves using DAQ and U2700A Series modular products. Slot 1 Slot 2 Slot 3 Slot 4 & Slot 5 Slot 6 DAQ U2701A/U2702A U2761A U2722A DAQ Supported configurations Configuration 1 M = T0 – T7 S = T0 S = T3 S = T7 S = T0 – T7 Configuration 2 None M = T1 S = T1 S = T1 None Configuration 3 M = T0 – T7 None None None S = T0 – T7 Not supported configurations Configuration 1[1] M = T0 – T7 M = T1 S = T1 S = T2 None Configuration 2[2] S = T0 – T7 M = T1 S = T1 S = T2 None Configuration 3[2] S = T0 – T7 M = T1 S = T1 S = T1 None Configuration 4[2] S = T0 – T7 M = T0 – T7 S = T0 S = T0 None M — Master, S — Slave, T0~T7 — Trigger bus (TRIG [0..7]), * — Star Trigger [1] Multiple Master is not allowed with DAQ set as Master. [2] U2700A Series modular devices should not be configured as Master. U2781A User’s Guide Features and Functions Multiple Master–multiple Slaves In this configuration, groups of single Master-multiple Slaves are allowed in order to perform multiple synchronizations simultaneously. This configuration is only supported by U2700A Series modular products. Figure 2-7 Multiple Master–multiple Slave triggering Table 2-4 shows some examples of supported and not supported configurations. Example of configurations for multiple Master–multiple Slaves. U2781A User’s Guide Features and Functions Table 2-4 Example of configurations for multiple Master–multiple Slaves Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 & Slot 6 U2701A U2702A U2761A U2751A U2722A Supported configurations Configuration 1 M = T0 S = T0 S = T0 None S = T0 Configuration 2 S = T1 M = T1 None None S = T1 Configuration 3 M = T0 M = T1 S = T0 None S = T1 Configuration 4 *(Out) S = T1 * (In) None S = T1 M = T1 Configuration 5 *(Out) * (In) * (In) None * (In) Not supported configurations Configuration 1[1] M = T0 M = T0 S = T0 None S = T0 Configuration 2[2] M = T3 S = T3 M = T4 None S = T4 S = T4 Configuration 3[3] M = T0 S = T0 S = T0 None S = T1 S = T1 Configuration 4[4] *(Out) * (In) None None None M = T1 S = T1 M — Master, S — Slave, T0~T7 — Trigger bus (TRIG [0..7]), * — Star Trigger [1] Same trigger line is not allowed for multiple Master configuration. [2] Slave device not allowed to occupy two trigger lines. [3] Not allowed to have both Master and Slave configuration for a device. [4] Not allowed to have Star Trigger and Slave mode for a device. U2781A User’s Guide Features and Functions System Reference Clock The 10 MHz reference clock can come from two sources; internal backplane oscillator and external clock source. The internal oscillator on the USB backplane supplies an independent 10 MHz system reference clock to each of the USB slot. This 10 MHz reference clock is driven through an independent buffer. Refer to Figure 2-3 for the block diagram. Every clock trace is in equal distance to ensure that the distance of the slot to the slot skew is minimized. Users can use this common reference clock signal to synchronize multiple modules in a measurement or control system. The default SCPI command of ACQuire:RSIGnal AUTO will scan through and detect if there is any valid clock source from the external BNC connector. If none is found, then the internal 10 MHz clock source will be used. The SCPI command below wi...