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AC Characteristics GND = 0 V , VDD=1.8Vto5.5V,Ta= .40 °C to +85 °C Item Symbol Condition Min. Typ. Max. Unit SCL clock frequency fSCL 400 kHz Start condition setup time tSU;STA 0.6 .s Start condition hold time tHD;STA 0.6 .s Data setup time tSU;DAT 100 ns Data hold time tHD;DAT 0 ns Stop condition setup time tSU;STO 0.6 .s Bus idle time between start condition and stop condition tBUF 1.3 .s Time when SCL = "L" tLOW 1.3 .s Time when SCL = "H" tHIGH 0.6 .s Rise time for SCL and SDA tr 0.3 .s Fall time for SCL and SDA tf 0.3 .s Allowable spike time on bus tSP 50 ns FOUT duty tW /t VDD = 2.4 V . 5.5 V 50% of VDD level 45 50 55 % Timing chart tHD ; DAT tSU ; DAT tHD ; STA tLOW tHIGH 1 / fSCL tr tf tSU ; STA SDA SCL START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) ACK (A) Protocol tBUF tSU ; STO STOP CONDITION (P) START CONDITION (S) (P) (A) tHD ; STA tSU ; STA (S) BIT 0 LSB (R/W) (S) tSP Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop condition after access should be completed within 0.95 seconds. If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus timeout function. Page - 4 MQ372-02 RX -8581 SA /JE/NB 8. Use Methods 8.1. Overview of Functions 1) Clock functions This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. . For details, see "8.2. Description of Registers". 2) Fixed-cycle interrupt generation function The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 .s and 4095 minutes. When an interrupt event is generated, the /INT pin goes to low level ("L") and "1" is set to the TF bit to report that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low level to Hi-Z). . For details, see "8.3. Fixed-cycle Interrupt Function". . 3) Time update interrupt function The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (a fixed value) after the interrupt occurs. . For details, see "8.4. Time Update Interrupt Function". 4) Alarm interrupt function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred. . For details, see "8.5. Alarm Interrupt Function". 5) 32.768-kHz clock output The 32.768-kHz clock (with precision equal to that of the built-in crystal oscillator) can be output via the FOUT pin. The FOUT pin is a CMOS output pin which can be set for clock output when the FOE pin is at high level and for low-level output when the FOE pin is at low level. 6) Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since neither SCL nor SDA includes a protective diode on the VDD side, a data interface between hosts with differing supply voltages can still be implemented by adding pull-up resistors to the circuit board. The SCL's maximum clock frequency is 400 kHz (when VDD . 1.8 V), which supports the I2C bus's high-speed mode. . For further description of data read/write operations, see "8.6 Reading/Writing Data via the I2C Bus Interface". Page - 5 MQ372-02 RX -8581 SA /JE/NB 8.2. Description of Registers 8.2.1. Register table Remark SEC .3 MIN .3 HOUR • .3 WEEK .3 DAY • .3 MONTH • • .3 . .4 . .4 0 .4 . .4 TE • .1, .3, .5 Flag Register • AF VLF .1, .2, .3 Control Register • AIE .3 Note When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before using the module. Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or time data is incorrect. .1) During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1". . At this point, all other register values are undefined, so be sure to perform a reset before using the module. .2) Only a "0" can be written to the UF, TF, AF, or VLF bit. .3) Any bi...

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