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Manafacture: Cypress
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manual abstract
BiCMOS technology Functional Description The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are independent and can operate simultaneously at different rates. The transmit channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. The receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0104TRB chips. The CYV15G0104TRB satisfies the SMPTE 259M and SMPTE 292M compliance as per SMPTE EG34-1999 Pathological Test Requirements. As a second-generation HOTLink device, the CYV15G0104TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. The transmit (TX) channel of the CYV15G0104TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ECL (PECL) compatible differential trans- mission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. The receive (RX) channel of the CYV15G0104TRB HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. Also, the recovered serial data is deserialized and presented to the destination host system. The transmit and receive channels contain an independent BIST pattern generator and checker, respectively. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links. Figure 1. HOTLink II™ System Connections Video Coprocessor 10 10 Video Coprocessor10 10 Serial Links Independent CYV15G0104TRB Independent Device Device Channel CYV15G0104TRB Channel Reclocked Output Reclocked Output Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-02100 Rev. *B Revised July 8, 2005 [+] Feedback CYV15G0104TRB The CYV15G0104TRB is ideal for SMPTE applications where format routers, switchers, format converters, SDI monitors, different data rates and serial interface standards are cameras, and camera control units. necessary for each channel. Some applications include multi CYV15G0104TRB Serializer and Reclocking Deserializer Logic Block Diagram x10 Serializer TX x10 Deserializer Reclocker RX TXDB[ 9: 0] RXDA[9:0] TOUTB1± TOUTB2± ROUTA1± ROUTA2± INA1± INA2± Phase Align Buffer REFCLKB± TRGCLKA± Document #: 38-02100 Rev. *B Page 2 of 27 [+] Feedback CYV15G0104TRB INA1+ INA1– INA2+ INA2– INSELA Clock & Data RecoveryPLL Shifter LFIA 10 RXDA[9:0] Receive SignalMonitor OutputRegister RXCLKA+ RXCLKA– .2 JTAG Boundary Scan Controller TDO TMS TCLK TDI RESET Reclocking Deserializer Path Block Diagram TRST RXPLLPDA SPDSELA ULCA RXRATEA 10 BIST LFSR10 RXBISTA[1:0] LDTDEN SDASEL[2..1]A[1:0] ROUTA1+ ROUTA1– ROUTA2+ ROUTA2– ROE[2..1]A Bit-Rate Clock Character-Rate Clock Reclocker RECLKOA Register Recovered Character Clock Recovered Serial Data TRGCLKA x2 TRGRATEA REPDOA BISTSTA Clock MultiplierOutput PLL ROE[2..1]A Shifter Serializer Path Block Diagram TXRATEB InputRegister SPDSELB REFCLKB+ REFCLKB– TXCLKB Bit-Rate Clock Character-Rate Clock TOUTB1+ TOUTB1– TOUTB2+ TOUTB2– Phase-AlignBuffer Transmit PLL Clock Multiplier TOE[2..1]B TXCKSELB = Internal Signal TXERRB TXCLKOB TXDB[9:0] 10 10 PABRSTB TOE[2..1]B 10 BIST LFSR10 TXBISTB 10 WREN ADDR[2:0] DATA[6:0] Device Configuration and Control Block Diagram = Internal Signal RXRATEA RXPLLPDA TXRATEB TXCKSELB TOE[2..1]B PABRSTB Device Configuration and Control Interface SDASEL[2..1]A[1:0] RXBISTA[1:0] TXBISTB ROE[2..1]A TRGRATEA CYV15G0104TRB INA1+ INA1– INA2+ INA2– INSELA Clock & Data RecoveryPLL Shifter LFIA 10 RXDA[9:0] Receive SignalMonitor OutputRegister RXCLKA+ RXCLKA– .2 JTAG Boundary Scan Controller TDO TMS TCLK TDI RESET Reclocking Deserializer Path Block Diagram TRST RXPLLPDA SPDSELA ULCA RXRATEA 10 BIST LFSR10 RXBISTA[1:0] LDTDEN SDASEL[2..1]A[1:0] ROUTA1+ ROUTA1– ROUTA2+ ROUTA2– ROE[2..1]A Bit-Rate Clock Character-Rate Clock Reclocker RECLKOA Register Recovered Character Clock Recovered Serial Data TRGCLKA x2 TRGRATEA REPDOA BISTSTA Clock ...