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manual abstract
Resolution Status. Fix planned for a future revision. Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E—December 2002 17 Deadlock May Occur in a Two-Processor System in the Presence of Probe to Memory- Mapped I/O Products Affected. A0, A2, A5 Normal Specified Operation. Processor should not hang. Non-conformance. In a multiprocessor system, if one processor (A) is continuously writing to a cacheable memory-mapped I/O block while the other processor (B) is trying to read the same cacheable I/O block, and at the same time both processors are also trying to write a different memory-based cache block, then processor B may hang. Should this occur and processor A fields an interrupt, the deadlock will be resolved. Potential Effect on System. System will hang or exhibit performance degradation. Suggested Workaround. The current processor design assumes that memory-mapped I/O is incoherent and does not handle all deadlock cases. System logic should not generate probes for memory mapped I/O addresses. Resolution Status. No fix planned. Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 18 Processor May Issue Non-Connect Bus Cycle After FID Special Cycle Products Affected. A0, A2 Normal Specified Operation. The first processor cycle after a FID Change special cycle should be a Connect special cycle. Non-conformance. In rare circumstances, a processor victim write may be pending inside the processor when the FID Change special cycle is issued. Several bus clocks later, the WrVictimBlk command for the victim will be issued. This violates the specification, which states that all processor-based commands should be finished before the FID change special cycle. Potential Effect on System. The core logic may become confused. Suggested Workaround. System core logic can wait for numerous bus clocks after receiving the FID change special cycle before attempting to disconnect in order to generate a window sufficiently large enough to allow the WrVictimBlk transaction to take place prior to the disconnect. Resolution Status. Fix planned for a future revision. Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E—December 2002 19 Processor Does Not Support Reliable Microcode Patch Mechanism Products Affected. A5 Normal Specified Operation. The processor should function properly after a microcode patch is loaded. Non-conformance. The processor has the patch RAM BIST function disabled. Since BIST is not run on the patch RAM, reliable operation of the patch RAM cannot be guaranteed. Therefore it should not be used. Potential Effect on System. When a microcode patch is loaded, the system may not behave properly. Suggested Workaround. Do not load a microcode patch. Resolution Status. Fix planned for a future revision. Preliminary Information 24332E—December 2002 AMD Athlon™ Processor Model 6 Revision Guide 20 Processor Performance Counters Do Not Count Some x86 Instructions Products Affected. A0, A2, A5 Normal Specified Operation. The processor should count all x86 instructions when programmed to do so. Non-conformance. There are two types of uncounted instructions. One set of instructions is always uncounted. Another set of instructions are uncounted only if a certain data dependency exists. Instructions never counted are: RDMSR, WRMSR, FSTENV, FSAVE, FLDENV, FPTAN, FYL2XP1, FCLEX, LLDT, LTR, MOV CRx, LGDT, LIDT, INVLPG, INVD, WBINVD, MOV DRx, CPUID, and SFENCE. Instructions that are uncounted only when certain data dependencies exist are: ¦ LAR, LSL, VERR, VERW if they clear the Zero Flag ¦ FXSAVE, FXRSTOR if FERR is changed ¦ FPU instructions with exceptional data conditions ¦ IO instructions that detect an interrupt ¦ POPF with the trap flag =1 ¦ POPFD and PUSHFD with IOPL not equal 3 and Virtual Mode enabled ¦ POPFD when Alignment Check is being enabled ¦ MOV SS with the trap flag =1 ¦ Segment Loads that generate accessed bit exceptions ¦ STI with the trap flag or the interrupt flag already a 1 ¦ CLTS with the CR0.TS flag =1 ¦ LMSW that changes any bit Potential Effect on System. Performance counter may under count the actual number of x86 instructions. Suggested Workaround. Versions of the AMD Athlon™ processor not affected by this erratum may be used to gather instruction counts. Resolution Status. No fix planned. Preliminary Information AMD Athlon™ Processor Model 6 Revision Guide 24332E—December 2002 21 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution Products Affected. A0, A2, A5 Normal Specified Operation. Self-modifying code sequences should be correctly detected and handled in a manner consistent with canonical results; stale code should not be executed. Non-conformance. The following scenario can result in a one-time execution of stale instructions: 1. A speculative store instruction initiates a request (R) to modify a 64-byte cache line with address A, which currently resides within the L1 ins...