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manual abstract
1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel, 10-bit ADC Differential mode with selectable gain at 1x, 10x or 200x – Byte-oriented Two-wire Serial Interface – Two Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby • I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF – 44-pad DRQFN – 49-ball VFBGA • Operating Voltages – 1.8 - 5.5V • Speed Grades for ATmega164PA/324PA/644PA/1284P – 0 - 20MHz @ 1.8 - 5.5V • Power Consumption at 1 MHz, 1.8V, 25°C – Active: 0.4 mA – Power-down Mode: 0.1.A – Power-save Mode: 0.6.A (Including 32 kHz RTC) Note: 1. See ”Data Retention” on page 9 for details. 8-bit Microcontroller with 16/32/64/128K Bytes In-System Programmable Flash ATmega164PA ATmega324PA ATmega644PA ATmega1284P Summary Rev. 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P 1. Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164PA/324PA/644PA/1284P Figure 1-1. Pinout PDIP (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6 TQFP/VQFN/QFN/MLF (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31) PB4 (SS/OC0B/PCINT12) (PCINT27/TXD1/INT1) PD3 PB3 (AIN1/OC0A/PCINT11) (PCINT28/XCK1/OC1B) PD4 PB2 (AIN0/INT2/PCINT10) (PCINT29/OC1A) PD5 PB1 (T1/CLKO/PCINT9) (PCINT30/OC2B/ICP) PD6 PB0 (XCK0/T0/PCINT8) (PCINT31/OC2A) PD7 GND VCC VCC GND PA0 (ADC0/PCINT0) (PCINT16/SCL) PC0 PA1 (ADC1/PCINT1) (PCINT17/SDA) PC1 PA2 (ADC2/PCINT2) (PCINT18/TCK) PC2 PA3 (ADC3/PCINT3) (PCINT19/TMS) PC3 PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P ATmega164PA/324PA/644PA/1284P 2 Pinout - DRQFN for ATmega164PA/324PA/644PA Figure 1-2. DRQFN - Pinout Top view Bottom view A24B20A23B19A22B18A21B17A20B16A19 A19B16A20B17A21B18A22B19A23B20A24 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13 A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 A7 B6 A8 B7 A9 B8A10 B9A11 B10A12 A12B10A11B9A10B8 A9 B7 A8 B6 A7 Table 1-1. DRQFN - Pinout A1 PB5 A7 PD3 A13 PC4 A19 PA3 B1 PB6 B6 PD4 B11 PC5 B16 PA2 A2 PB7 A8 PD5 A14 PC6 A20 PA1 B2 RESET B7 PD6 B12 PC7 B17 PA0 A3 VCC A9 PD7 A15 AVCC A21 VCC B3 GND B8 VCC B13 GND B18 GND A4 XTAL2 A10 GND A16 AREF A22 PB0 B4 XTAL1 B9 PC0 B14 PA7 B19 PB1 A5 PD0 A11 PC1 A17 PA6 A23 PB2 B5 PD1 B10 PC2 B15 PA5 B20 PB3 A6 PD2 A12 PC3 A18 PA4 A24 PB4 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P 1.3 Pinout - VFBGA for ATmega164PA/324PA/644PA Figure 1-3. VFBGA - Pinout 1 234567 Top view 765432 Bottom view 1 A B C D E F G A B D E F G Table 1-2. BGA - Pinout 1 2 3 4 5 6 7 A GND PB4 PB2 GND VCC PA2 GND B PB6 PB5 PB3 PB0 PA0 PA3 PA5 C VCC RESET PB7 PB1 PA1 PA6 AREF D GND XTAL2 PD0 GND PA4 PA7 GND E XTAL1 PD1 PD5 PD7 PC5 PC7 AVCC F PD2 PD3 PD6 PC0 PC2 PC4 PC6 G GND PD4 VCC GND PC1 PC3 GND 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P 2. Overview The ATmega164PA/324PA/644PA/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164PA/324PA/644PA/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PA7..0 PB7..0 CPU...