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(0 dBm to +13 dBm) Square wave: 0.2 Vpk-pk to 2.8 Vpk-pk into 50 . — Maximum Input Overload ±10 V — Input Impedance 50 . — Input Coupling AC — © National Instruments Corporation 19 NI 5421 Specifications PFI 0 and PFI 1 PFI 0 and PFI 1 Table 6. Specification Value Comments Connectors Two SMB (jack) — Direction Bi-directional — Frequency Range DC to 105 MHz — As an Input (Trigger) Destinations Start Trigger — Maximum Input Overload –2 V to +7 V — VIH 2.0 V VIL 0.8 V Input Impedance 1 k. As an Output (Event) Sources 1. Sample Clock divided by integer K (1 . K . 4,194,304) 2. Sample Clock Timebase (100 MHz) divided by integer M (2 . M . 4,194,304) 3. PLL Reference Clock 4. Marker 5. Exported Start Trigger (Out Start Trigger) — Output Impedance 50 . — Maximum Output Overload –2 V to +7 V — NI 5421 Specifications 20 ni.com Table 6. (Continued) Table 6. (Continued) Value Comments VOH Minimum: 2.9 V (open load), 1.4 V (50 . load) Output drivers are +3.3 V TTL compatible. Measured with a 1 m cable. VOL Maximum: 0.2 V (open load), 0.2 V (50 . load) Rise/Fall Time (20% to 80%) .2.0 ns Load of 10 pF. © National Instruments Corporation 21 NI 5421 Specifications DIGITAL DATA & CONTROL (DDC) Optional Front Panel Connector Table 7. Specification Value Comments Connector Type 68-pin VHDCI female receptacle — Number of Data Output Signals 16 — Control Signals 1. DDC CLK OUT (clock output) 2. DDC CLK IN (clock input) 3. PFI 2 (input) 4. PFI 3 (input) 5. PFI 4 (output) 6. PFI 5 (output) — Ground 23 pins — Output Signal Characteristics (Includes Data Outputs, DDC CLK OUT, and PFI<4..5>) Signal Type LVDS (Low-Voltage Differential Signal) — Signal Characteristics Minimum Typical Maximum 1. Tested with 100 . differential load. 2. Measured at the front panel. 3. Load capacitance <10 pF. 4. Driver and receiver comply with ANSI/TIA/ EIA-644. 5. Rise time is 20% to 80%. VOH — 1.3 V 1.7 V VOL 0.8 V 1.0 V — Differential Output Voltage 0.25 V — 0.45 V Output Common-Mode Voltage 1.125 V — 1.375 V Rise/Fall Time — 0.8 ns 1.6 ns NI 5421 Specifications 22 ni.com Table 7. (Continued) Table 7. (Continued) Value Comments Output Signal Characteristics (Continued) Output Skew Typical: 1 ns, maximum 2 ns. Skew between any two outputs on the DIGITAL DATA & CONTROL front panel connector. — Output Enable/Disable Controlled through the software on all Data Output Signals and Control Signals collectively. When disabled, the outputs go to a high-impedance state. — Maximum Output Overload –0.3 V to +3.9 V — Input Signal Characteristics (Includes DDC CLK IN and PFI<2..3>) Signal Type LVDS (Low-Voltage Differential Signal) — Input Differential Impedance 100 . — Maximum Output Overload –0.3 V to +3.9 V — Signal Characteristics Minimum Maximum — Differential Input Voltage 0.1 V 0.5 V Input Common Mode Voltage 0.2 V 2.2 V DDC CLK OUT Clocking Format Data outputs and markers change on the falling edge of DDC CLK OUT. — Frequency Range Refer to the Sample Clock section for more information. — Duty Cycle 40% to 60% — Jitter 40 ps rms — © National Instruments Corporation 23 NI 5421 Specifications Table 7. (Continued) Table 7. (Continued) Value Comments DDC CLK IN Clocking Format DDC Data Output signals change on the rising edge of DDC CLK IN. — Frequency Range 10 Hz to 105 MHz — Input Duty Cycle Tolerance 40% to 60% — Input Jitter Tolerances 300 ps pk-pk of Cycle-Cycle Jitter, and 1 ns rms of Period Jitter. — Start Trigger Table 8. Specification Value Comments Sources 1. PFI<0..1> (SMB front panel connectors) 2. PFI<2..3> (DIGITAL DATA & CONTROL front panel connector) 3. NI PXI-5421—PXI_Trig<0..7> (backplane connector) NI PCI-5421—RTSI<0..7> 4. NI PXI-5421—PXI Star trigger (backplane connector) 5. Software (use function call) 6. Immediate (does not wait for a trigger). Default. — Modes 1. Single 2. Continuous 3. Stepped 4. Burst — Edge Detection Rising — Minimum Pulse Width 25 ns. Refer to ts1 at NI Signal Generators Help»Devices» NI 5421»NI -5421»Triggering»Trigger Timing. — NI 5421 Specifications 24 ni.com Table 8. (Continued) Table 8. (Continued) Value Comments Delay from Start Trigger to CH 0 Analog Output Interpolation Factor Typical Delay Refer to ts2 at NI Signal Generators Help»Devices» NI 5421» NI -5421» Triggering» Trigger Timing. Digital Interpolation Filter disabled. 43 Sample Clock Periods + 110 ns 2 57 Sample Clock Periods + 110 ns 4 63 Sample Clock Periods + 110 ns 8 64 Sample Clock Periods + 110 ns Delay from Start Trigger to Digital Data Output 40 Sample Clock periods + 110 ns. — Trigger Exporting Exported Trigger Destinations A signal used as a trigger can be routed out to any destination listed in the Destinations specification of Table 9. — Exported Trigger Delay 65 ns (typical). Refer to ts3 at NI Signal Generators Help» Devices»NI 5421»NI -5421»Triggering»Trigger Timing. — Exported Trigger Pulse Width >150 ns. Refer to ts4 at NI Signal Generators Help» Devices»NI 5421»NI -5421»Triggering»Trigger Timing. — © National Inst...

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